Today, the Plasma technology makes possible to achieve flat colour panel of large size (out of the CRT limitations) and with very limited depth without any viewing angle constraints. Like CRT (Cathode Ray Tube) technology, PDP is a technology that generates its own light. In the same way, both technologies use a power management (or brightness regulation) circuit which allows a higher peak white brightness value than a full white value.
The CRT screens use a so called ABL (for Average Beam-current Limiter) circuit, which is implemented by analog means usually in the video controller, and which decreases video gain as a function of average luminance usually measured over an RC stage.
The plasma display panels use a so called APL (for Average Power Level) control circuit that generates less or more sustain pulses as a function of the average power level of the displayed picture. The APL control starts from the reflection that for larger peak white luminance values in plasma displays more sustain pulses are necessarily required. On the other hand, more sustain pulses correspond also to a higher power consumption of the PDP. Thus the solution is a control method which generates more or less sustain pulses as a function of the average picture power, i.e. it switches between different modes with different power levels. Such an APL control circuit is described in the international patent application WO 00/46782. For pictures having relatively low picture power, i.e. a lot of pixels with relatively low luminance value, a mode will be selected which uses a high number of sustain pulses to create the different video levels because the overall power consumption will be limited due to a great amount of pixels with low luminance value. For pictures having relatively high picture power, i.e. a lot of pixels with relatively high luminance value, a mode will be selected which uses a low number of sustain pulses to create the different video levels because the overall power consumption will be high due to a great amount of pixels with high luminance value. Thus, a plurality of power level modes can be defined for a good management of the power consumption.
The APL control is implemented as follows: first the average video level of the input signal after de-gamma is computed. This value is a good estimation of the total luminance power required for reproducing the input picture. Secondly, by means of a look-up table, the total number of sustain pulses that can be generated for the input picture to keep the power consumption in an authorized range is determined and a corresponding subfield organisation is simultaneously selected. As described in the international patent application WO 00/46782, the sub-field organisations can vary in respect to one or more of the following characteristics:                the number of sustain pulses;        the number of sub-fields;        the sub-field positioning.        
As mentioned before, this APL control circuit allows a higher peak-white value without overloading the set power supply. However, this solution is not optimal in some operation conditions. For example, if the PDP is connected to a video source where the video range is inferior to the nominal range (for instance if the input video range is 0 to 160 and the nominal range is 255 for an 8-bit range), there are some video levels that are never used and some supply power is so wasted in generating sustain pulses that produce no light. Indeed, as the sustain pulses are generated simultaneously for the whole panel, even if a subfield is never used, it consumes energy.